When fabricating a CMOS device that includes metal gate electrodes, a replacement gate process may be used to form gate electrodes having different metals, where one metal provides a work function that is appropriate for PMOS devices and a different metal provides a work function that is appropriate for NMOS devices. Typically, in that process, a polysilicon layer bracketed by a pair of spacers is removed to create a trench region between the spacers. The trench is filled with a first metal, for say the NMOS devices. A second polysilicon layer is then removed, and replaced with a second metal that differs from the first metal used for the PMOS devices.
Replacement gate processes can be embodied as gate dielectric first or gate dielectric last. Due to reliability considerations, gate dielectric first is generally used. However, as known in the art, gate dielectric first processes lack high selectivity in the polysilicon etch process to the underlying gate dielectric as well as the sidewall films (e.g. poly oxide) and the trench isolation fill material in the case of trench isolation (e.g. STI), which generally results in one or more polysilicon etch induced problems. Such induced problems include, but are not limited to, unreliable gate dielectrics, unintended gate CD bias (between NMOS to PMOS devices) and metal-1 (M1) electrical shorts due to the creation or deepening of trench isolation divots at the active area boundary. Moreover, it is generally not possible to remove p-doped polysilicon and n-doped polysilicon at the same time using a single etch due to significant differences in their respective etch rates. Accordingly, there is a need for an improved dielectric first replacement metal gate process for fabricating a semiconductor device and improved integrated CMOS circuits therefrom.